1. Technical Field
The invention disclosed broadly relates to memory technology and more particularly relates to improved FET memory arrays.
2. Background Art
The segmented precharge architecture is an extension of the segmented word line architecture (also termed double word line scheme, block oriented die architecture, and divided word line architecture). This scheme reduces power dissipation by reducing the number of active columns (bit lines). The vast majority of SRAMs equal to or larger than 64K use the segmented word line architecture.
FIG. 1 shows a typical prior art implementation of the segmented word line architecture. The memory is broken into two sections 1 and 2. The row addresses are decoded and select one of 128 main word lines WL0 to WL127. The section addresses are decoded and select one of two sections 1' or 2' to enable. The main word line e.g. WL0 and the section enable 20 are combined via AND gates, and select one word line 24 in one section 1' of the chip. Notice that the chip contains a total of 64 columns (two sections 1' and 2' with 32 columns each), but only 32 columns are active at any time. This scheme can be extended to any number of blocks.
The typical prior art implementation of the precharge scheme is also shown in FIG. 1. The Address Transition Detect (ATD) circuit generates a pulse when any of the row or section addresses change. The pulse generated by the ATD circuit disables the row decoder, thus deactivating all word lines, and precharging (equalizing) the bit lines. At the completion of the ATD pulse, the bit line precharge is turned off and a new word line is activated. Note that the start of the read access (when new word line goes up) is delayed by the ATD pulse (see FIG. 2).
Since generating an ATD pulse extends the read cycle, the ATD pulse should be generated only when absolutely necessary. For this reason the column addresses do not feed the ATD circuit, and changing a column address does not cause an ATD pulse. Eliminating the ATD pulse from the column access, produces a column access that is faster than either a row or section access. This fast column access is termed static page mode. For the typical prior art scheme shown in FIG. 1, the number of columns available in the static page mode is limited to the number of columns in a section (i.e., 32) regardless of the number of sections.
It is important to understand why changing a row or section address must cause an ATD pulse, while changing the column address does not. When a row address changes, the word line that is on turns off, and a word line that was previously off turns on. The voltage difference on the bit lines represents the value of the data stored in the cell whose word line is turning off. When the new word line turns on this voltage delta may over-drive the data in the new cell; thus writing data into the cell instead of reading it. In order to prevent writing into the new cell, the data from the old cell must be removed from the bit lines, i.e., the bit lines must be precharged.
A similar situation exists when a section address changes. When a section is not selected, its bit lines are floating in the prior art. The bit lines are floating for varying amounts of time depending on how frequently the section is accessed. Junction leakage, capacitance coupling, alpha particles, and single event upset (SEU) can produce a voltage delta on the bit lines large enough to write into the cell during a read access. Thus, changing a section address must result in an ATD pulse to perform a precharge.
Also note, as shown in FIG. 1, the ATD pulse switches all bit line precharge devices simultaneously. This causes large current spikes which generate noise and can cause the voltage at the power pad to droop due to package (pin) inductance. In addition, in the typical scheme shown in FIG. 1, precharge is active only during the ATD pulse, a very small portion of the cycle; thus, most of the bit lines are floating.